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T6L37A
TOSHIBA CMOS Digital Integrated Circuits Silicon Monolithic
T6L37A
Source Driver for TFT LCD Panels
The T6L37A is a 64 gray-level and 300/309-channel-output source driver for TFT LCD panels. To meet the need for large-sized LCD panels, it allows a maximum operating frequency of 55 MHz. The device accepts 6-bit digital data inputs, which combined with the internal DA converter and 11 external power supplies allows display of up to 260,000 colors. Based on high-speed CMOS, the T6L37A offers both low power consumption and high-speed operation. The T6L37A allows configuration of an XGA-or SVGA-compatible, high-performance TFT LCD module.
Features
l Grayscale data : 18-bit digital (3 outputs x 6 bits) parallel transfer method, selectable write direction. : 300/309 outputs, 64 gray levels, DAC system, reference analog voltage : Max. 55 MHz : Digital power supply voltage..........3.0 to 3.6 V Analog power supply voltage..........4.5 to 5.5 V : -20 to 75C : Tape carrier package (TCP)
l Panel drive outputs l Fast operation l Power supply voltage l Operating temperature l Package
l Cascading multiple devices
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Block Diagram
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Pin Assignment
The above diagram shows the device's pin configuration only and does not necessarily correspond to the pad layout on the chip. Please contact Toshiba or our distributor for the latest TCP specification.
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Pin Function
Pin Name I/O Function Data transfer enable pin These pins, become active at the high signal, initiated the transferred data into the sampling register of the device. One is configured as an input and the other is configured as an output of which directions are determined by U/D as shown below. U/D DI/O DO/I I/O H L DI/O Input Output DO/I Output Input
When set for input A high on DI/O or DO/I is latched into the internal logic synchronously with the rising edge of CPH. When the internal circuit is in standby state, the device is ready to transfer data. The grayscale data is latched in sequentially, starting at the next rise of CPH. When set for output The pin is used to transfer the enable signal to the T6L37A at the next stage of the LCD driver. The pin enters standby state after outputting a high. Transfer direction select pin This pin controls the direction in which the data is transferred into the sampling register. Data is transferred synchronously with each rising edge of CPH in one of the following sequences: When U/D is high, data is transferred in the order D1 to D3, D4 to D6, D7 to D9, ...... When U/D is low, the direction is reversed to give D307 to D309, D304 to D306, D301 to D303, ...... The voltage applied to this pin must be a DC-level voltage that is either high or low. Sampling clock input This clock input is used to transfer grayscale data. Grayscale data bus The data inputs consist of 6-bit word for each three channel that are transferred in parallel at the rising edge of CPH. The relationship between the grayscale data and the weight of each bit is as follows: Grayscale data = 32 DFn + 16 DEn + 8 DDn + 4 DCn + 2 DBn + DAn (*) where n = 1 to 3 The relationship between the grayscale data and the output pins is as follows: DA1, DB1, DC1, DD1, DE1, DF1...D(3m-2) DA2, DB2, DC2, DD2, DE2, DF2...D(3m-1) DA3, DB3, DC3, DD3, DE3, DF3...D(3m) *where m = 1 to 103 Output select pin This signal selects either 300-pin mode or 309-pin mode for the LCD panel driver. When MODE = high, 300-output-pin mode is selected, in which case D151 through D159 are not used. (Voltages appearing at D151 through D159 are indeterminate.) When MODE = low, 309-output-pin mode is selected. This pin is internally pulled up in the chip. Data load input pin When a high voltage supply to the load input, the data is transferred from the Sampling register to the Load register synchronously at the rising edge of CPH. All 300 or 309 LCD panel drive pin outputs are simultaneously updated. The selected analog voltage corresponding to the data are send the LCD. Reference analog input pins These pins are used to input the voltage used for the DAC. Conditions : AVSS < V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 < AVDD or AVSS < V10 V9 V8 V7 V6 V5 V4 V3 V2 V1 V0 < AVDD O LCD panel drive pins Analog power supply pin Analog GND pin This pin must be at the same potential level as the digital GND pin. Digital power supply pin. Digital GND pin This pin must be at the same potential level as the analog GND pin.
U/D
I
CPH
I
DA1 to DA 3 DB1 to DB 3 DC1 to DC 3 DD1 to DD 3 DE1 to DE 3 DF1 to DF 3
I
MODE
I
LOAD
I
V0 to V10
D1 to D309 AVDD AVSS DVDD DVSS
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Device Operation
(1) Starting data transfer
A high input to the data transfer enable pin (DI/O or DO/I) is latched into the internal logic synchronously with the rising edge of CPH, setting the device ready to transfer data. Data transfer starts at the next rise of CPH (see Fig. 1-1 and 2-1). This enable pin must not be held for more than one CPH period.
(2) Data transfer method
The data is latched in from the grayscale bus to the sampling register (REG1) synchronously with each rising edge of CPH. Grayscale data for three outputs are latched into the device simultaneously in one transfer. Therefore, the data is latched in 300-output mode by performing 100 transfers, and data is latched in 309-output mode by performing 103 transfers. When the data loading is completed, the device enters a standby state.
(3) Terminating data transfer
The data transfer enable pin (DO/I or DI/O) output goes high synchronously with the rising edge of CPH one clock period before the last data is latched in. It is held high until the next rise of CPH (see Fig. 1-1 and 2-1). The output from this pin can be connected directly as input to the data transfer enable pin (DI/O or DO/I) of the next stage LCD driver. In this way, multiple devices can be easily cascaded to drive a large screen.
(4) Panel drive output
When a high voltage supplies to the load input, the data in the sampling register (REG1) is transferred to the load register (REG2) and the device starts updating output to the LCD panel drive pins. CPH must be held at the DC level for the duration from three CPH periods after a high input to LOAD is latched in until one clock period before CPH goes high after a high on the data transfer enable pin is latched in following a 1H period (see Fig. 1-2).
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(5) Reference power supply circuit
The connection between the device and the external reference power supply for Reference analog supply is configured with 7 or 8 resistors of the same specification in series (total of 64 resistor ladders).
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(6) Grayscale data and output voltages
The LCD drive output voltages are determined by the grayscale values and the 11 reverence analog inputs line voltages (V0 to V10). The three high-order data bits select a pair of reference analog voltages. Calculation of the output voltage involves multiplying a value derived from the selected reference analog values by a factor determined by the values of the three low-order bits and dividing by either seven or eight.
Three high-order data bits
DFn 0 0 0 0 1 1 1 1 DEn 0 0 1 1 0 0 1 1 DDn 0 1 0 1 0 1 0 1 Selected Reference Voltages V0 or V1 and V2 V2 and V3 V3 and V4 V4 and V5 V5 and V6 V6 and V7 V7 and V8 V8 and V9 or V10
Three low-order data bits
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Grayscale data and output voltages
Note:
Grayscale Data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH DFn DEn DDn DCn DBn DAn Output Voltage Grayscale Data 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH DFn DEn DDn DCn DBn DAn
n = 1 to 3
Output Voltage
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
V0 V2 + (V1 - V2) 6/7 V2 + (V1 - V2) 5/7 V2 + (V1 - V2) 4/7 V2 + (V1 - V2) 3/7 V2 + (V1 - V2) 2/7 V2 + (V1 - V2) 1/7 V2 V3 + (V2 - V3) 7/8 V3 + (V2 - V3) 6/8 V3 + (V2 - V3) 5/8 V3 + (V2 - V3) 4/8 V3 + (V2 - V3) 3/8 V3 + (V2 - V3) 2/8 V3 + (V2 - V3) 1/8 V3 V4 + (V3 - V4) 7/8 V4 + (V3 - V4) 6/8 V4 + (V3 - V4) 5/8 V4 + (V3 - V4) 4/8 V4 + (V3 - V4) 3/8 V4 + (V3 - V4) 2/8 V4 + (V3 - V4) 1/8 V4 V5 + (V4 - V5) 7/8 V5 + (V4 - V5) 6/8 V5 + (V4 - V5) 5/8 V5 + (V4 - V5) 4/8 V5 + (V4 - V5) 3/8 V5 + (V4 - V5) 2/8 V5 + (V4 - V5) 1/8 V5
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
V6 + (V5 - V6) 7/8 V6 + (V5 - V6) 6/8 V6 + (V5 - V6) 5/8 V6 + (V5 - V6) 4/8 V6 + (V5 - V6) 3/8 V6 + (V5 - V6) 2/8 V6 + (V5 - V6) 1/8 V6 V7 + (V6 - V7) 7/8 V7 + (V6 - V7) 6/8 V7 + (V6 - V7) 5/8 V7 + (V6 - V7) 4/8 V7 + (V6 - V7) 3/8 V7 + (V6 - V7) 2/8 V7 + (V6 - V7) 1/8 V7 V8 + (V7 - V8) 7/8 V8 + (V7 - V8) 6/8 V8 + (V7 - V8) 5/8 V8 + (V7 - V8) 4/8 V8 + (V7 - V8) 3/8 V8 + (V7 - V8) 2/8 V8 + (V7 - V8) 1/8 V8 V9 + (V8 - V9) 6/7 V9 + (V8 - V9) 5/7 V9 + (V8 - V9) 4/7 V9 + (V8 - V9) 3/7 V9 + (V8 - V9) 2/7 V9 + (V8 - V9) 1/7 V9 V10
Reference analog resistance rate (R0 = 2.31 kW) W
R0 1.00 R1 2.00 R2 2.77 R3 1.50 R4 0.90 R5 0.84 R6 0.66 R7 0.84 R8 1.42 R9 1.05
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Timing Diagrams
In 300-output mode
Fig. 1-1
Fig. 1-2
Note: Except for D151 to D159
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In 309 output mode
Fig. 2-1
Fig. 2-2
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Absolute Maximum Ratings (AVSS = DVSS = 0 V)
Characteristics Analog Supply Voltage Digital Supply Voltage Input Voltage Reference Analog Voltage Storage Temperature Symbol AVDD DVDD VIN V (0: 10) Tstg Rating -0.3 to 6.5 -0.3 to AVDD + 0.3 -0.3 to DVDD + 0.3 -0.3 to AVDD + 0.3 -55 to 125 Unit V V V V C Relevant Pin 3/4 3/4 3/4 V0 to V10 3/4
Recommended Operating Conditions (AVSS = DVSS = 0 V)
Characteristics Analog Supply Voltage Digital Supply Voltage Reference Analog Voltage-1 (Note 1) Symbol AVDD DVDD V1 to V9 V0 Reference Analog Voltage-2 (Note 1) V10 Driver Unit Output Voltage Operating Temperature Operating Frequency Output Load Capacitance VOUT Topr fCPH CL Test Condition Rating 4.5 to 5.5 3.0 to 3.6 AVSS + 0.1 to AVDD - 0.1 V1 to AVDD AVSS to V1 AVSS to V9 V9 to AVDD AVSS + 0.1 to AVDD - 0.1 -20 to 75 DC to 55 150 (max) V C MHz pF / PIN D1 to D309 CPH D1 to D309 V Unit V V V Relevant Pin
3/4 3/4 3/4
Case 1 Case 2 Case 1 Case 2
3/4 3/4 3/4 3/4
Note 1: The following shows the relative magnitude of each reference analog voltage: For case 1 AVSS < V10, Vd Vd - 1, V0 < AVDD (where d = 9 to 1) For case 2 AVSS < V0, Vd Vd + 1, V10 < AVDD (where d = 1 to 9)
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Electrical Characteristics
DC Characteristics (AVDD = 4.5 to 5.5 V, DVDD = 3.0 to 3.6 V, AVSS = DVSS = 0 V, Ta = -20 to 75C)
Characteristics Low Level Input Voltage High Level Low Level Output Voltage High Level VOH Ichg Output Current (Note 2) Resistance between Reference Analog Voltage Pins Output Voltage Deviation Leakage Current Standby Current Idis 3/4 VOUT = 0 V AVDD = 5 V VX = 1 V 3/4 3/4 3/4 fCPH = DC fCPH = 30 MHz 1H = 30 ms, no load Checkerboard pattern AVDD = 5.5 V fCPH = 30 MHz 1H = 30 ms, no load Checkerboard pattern DVDD = 3.6 V fCPH = 20 MHz 1H = 26.4 ms, no load Checkerboard pattern AVDD = 5.0 V fCPH = 20 MHz 1H = 26.4 ms, no load Checkerboard pattern DVDD = 3.0 V VIH VOL Symbol VIL Test Circuit Test Condition 3/4 Min 0 0.7 DVDD DVSS DVDD - 0.5 0.5 Typ. 3/4 3/4 3/4 3/4 Max 0.3 DVDD DVDD DVSS + 0.5 DVDD -0.15 3/4 mA D1 to D309 Unit Relevant Pin
3/4
3/4 IOL = 1.0 mA
V
Logic input
3/4
IOH = -1.0 mA
V
Logic output
3/4
3/4 3/4
30 20 3/4 0.0
RGMA VDO IIN IDSTB
3/4
3/4 3/4 -1.0 -5.0
3/4 3/4 1.0 5.0
kW mV mA mA
V0 to V10 D1 to D309 Logic input DVDD
3/4 3/4 3/4 3/4
AIDD Current Consumption (1) DIDD
3/4
4.0
7.0 mA
AVDD
3/4
3/4
6.0
8.0
DVDD
AIDD Current Consumption (2) DIDD
3/4
3/4
3.5
6.0 mA
AVDD
3/4
3/4
2.5
5.5
DVDD
Note 2: VX denotes the voltage applied to the LCD panel drive pin.
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AC Characteristics (AVDD = 4.5 to 5.5 V, DVDD = 3.0 to 3.6 V, DVSS = AVSS = 0 V, Ta = -20 to 75C)
Characteristics CPH Pulse Width H CPH Pulse Width L Enable Setup Time Enable Hold Time Enable Pulse Width H Data Setup Time Data Hold Time Output Delay Time 1 Output Delay Time 2 Symbol tCWH tCWL tsDI thDI tDWH tsDD thDD tpdDO tpdDE Test Circuit Test Condition Min 4.0 4.0 4.0 0 3/4 4.0 0 Typ. Max Unit ns ns ns ns CPH period ns ns ns ms ms CPH period ns CPH period
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
CL = 35 pF
3/4 3/4 3/4 3/4 3/4 3/4 3/4
CL = 2 kW + 75 pF 2 Target output voltage AVDD 0.1 CL = 2 KW + 75 pF 2 Target output voltage
3/4 3/4 3/4 3/4
1.0
3/4 3/4 3/4 3/4
3/4
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
3/4 3/4
14.0 3.0
3/4 3/4 3/4
1.0 7.0 2.0
Output Delay Time 3 LOAD Setup Time 1 LOAD Setup Time 2 LOAD Pulse Width H
tpdDX tsLD1 tsLD2 tLWH
10.0
3/4 3/4 3/4
3/4 3/4 3/4
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RESTRICTIONS ON PRODUCT USE
000707EBE
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * Polyimide base film is hard and thin. Be careful not to injure yourself on the film or to scratch any other parts with the film. Try to design and manufacture products so that there is no chance of users touching the film after assembly, or if they do , that there is no chance of them injuring themselves. When cutting out the film, try to ensure that the film shavings do not cause accidents. After use, treat the leftover film and reel spacers as industrial waste. * Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases this can cause the device to malfunction. This is especially true for devices in which the surface (back), or side of the chip is exposed. When designing circuits, make sure that devices are protected against incident light from external sources. Exposure to light both during regular operation and during inspection must be taken into account. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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